Integrated digital signal processor/general purpose CPU with shared internal memory

ABSTRACT

An integrated data processing platform for processing a digital signal that includes a general purpose processor and a digital signal processor (DSP) module. The DSP module recovers digital data from a digital signal utilizing a sequence of DSP operations selected by the general purpose processor. The general purpose processor processes the digital data recovered by the DSP module, but is also available to perform general purpose tasks. A shared internal memory array selectively provides information to the DSP module and to the general purpose processor. The information stored in the internal memory array includes operands utilized in the execution of the DSP algorithm and selected instructions and data utilized by the general purpose CPU either for controlling the execution of the DSP algorithm or for executing its own general purpose tasks. While in many applications the data processing system will include an analog front end that converts a modulated input signal received on an analog transmission channel to a corresponding digital signal for processing by the data processing system, the data processing system may also receive the digital signal directly from a digital source.

This is a continuation of application Ser. No. 08/011,102 filed on Jan.29, 1993, now abandoned, which is a continuation of application Ser. No.07/467,148 filed on Jan. 18, 1990 now abandoned.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to data processing systems and,in particular, to a processing platform that provides integrated generalpurpose and digital signal processing (DSP) capabilities for recoveringand processing digital data utilizing an internal shared memoryresource.

2. Discussion of the Prior Art

The basic function of any communications system is to transmitinformation over a communication channel from an information source to adestination as fast and as accurately as possible.

There are two general types of information sources. Analog sources, suchas a telephone microphone, generate a continuous signal. Digitalsources, such as a digital data processing system, generate a signalthat consists of a sequence of pulses.

Communications channels that are designed to transmit analog signals(e.g., the telephone network) have characteristics which make itdifficult for them to transmit digital signals. To permit thetransmission of digital pulse streams over an analog channel, it isnecessary to utilize the digital data pulses to modulate a carrierwaveform that is compatible with the analog transmission channel.

The equipment that performs the required modulation is generallyreferred to as a “MODEM”. The term “MODEM” is an acronym forMOdulator-DEModulator, since one piece of equipment typically includesthe capability not only to modulate transmitted signals, but also todemodulate received signals to recover the digital data from themodulated analog carrier waveform.

While passing through the transmission channel, the modulated carrierwaveform suffers from distortion introduced both by the system itselfand by noise contamination. Thus, one of the tasks of the modem'sdemodulation function is to filter the signal received from thetransmission channel to improve the signal-to-noise ratio. Thedemodulator also retrieves timing information from the received signalto provide sampling points for recovering the digital data. Thedemodulator may also condition the data in other ways to make itsuitable for additional processing.

In a conventional modem, the signal filtering, sampling and conditioningtasks are performed by three functional units: analog-to-digitalconversion circuitry (“analog front end”) that converts the receivedmodulated carrier waveform to a digitized replica, a digital signalprocessor (DSP) that recovers the digital data from the digitizedreplica, and a control function for controlling both the analog frontend and the digital signal processor. The digital signal processorrecovers the data by implementing a signal conditioning and datarecovery algorithm that is specific to the type of data being received.

For example, the digital signal processor function in a facsimile (fax)machine modem implements a special purpose algorithm that can only beused for recovering the digital fax data. In the case of a fax system,the data to be recovered is a digital bit map that corresponds to thetransmitted hard copy image and which has been compressed to facilitateefficient transmission. The algorithm implemented by the digital signalprocessor function of the receiving fax machine's modem is a dedicated“fax” algorithm that has been designed specifically for accuratelyrecovering the compressed bit map. It cannot recover digital data in aformat other than a compressed bit map, e.g. voice mail data or datamodem applications. A different digital signal processor implementing adifferent dedicated “voice mail” or “data modem” algorithm is needed foreach of these other applications.

As shown in FIG. 1, a conventional fax machine architecture may bepartitioned into two major functional blocks: (1) a spectral purpose faxmodem block of the type described above for recovering a compressed bitmap from a modulated circuit waveform and (2) a general purposeprocessor block for performing those tasks require to convert thecompressed bit map to a corresponding hard copy image.

A well known example of a special purpose fax modem block is theRockwell R96DFX MONOFAX® modem chip, the so-called “Rockwell Module”. Inthe Rockwell Module, the incoming modulated carrier waveform receivedfrom an analog channel, i.e., a telephone line, is processed by ananalog front end which generates a digitized replica of the analogsignal; that is, the analog front end generates a digital reading of theinput voltage level. A dedicated fax digital signal processor thenperforms the adaptive filtering, signal sampling, synchronization andcarrier phase/frequency tracking required to reconstruct the compressedfacsimile bit map from the digitized replica provided by the analogfront end. The recovered bit map is then provided to the general purposeprocessor block which performs the additional processing functionsrequired for printing the transmitted image. That is, the generalpurpose processor block controls and performs the data decompression,decoding, imaging and printing functions necessary to generate a hardcopy reconstruction of the recovered bit map.

To transmit an image, the fax machine shown in FIG. 1 performs theabove-described steps in reverse order. The general purpose processorblock controls and performs the conversion of the hard copy image to acorresponding compressed bit map. The compressed bit map is thenprovided to the special purpose fax modem block which utilizes the bitmap to modulate a carrier waveform which is transmitted over the analogchannel to a destination fax machine.

A modem architecture similar to that of the Rockwell Module is alsoprovided by the Yamaha YM7109 FAX modem LSI chip.

The fax machine architecture exemplified by the Rockwell Module and theYamaha modem chip, that is, a special purpose fax modem block incombination with a separate general purpose processor block, suffersfrom a number of disadvantages. First, the system requires two separateprocessor functions: the special purpose DSP function of the modem blockfor recovering the compressed bit map and the general purpose processingand control functions of the general purpose processor block forperforming the remaining tasks required to convert the compressed bitmap to hard copy. Since there are periods of time when no facsimiletransmissions are being received, the system's full processingcapability is greatly underutilized. Furthermore, the DSP functions ofthe modem block are dedicated to a particular application, in this case,facsimile reception/transmission. That is, as stated above, the DSPalgorithm utilized to recover the incoming data is fixed; aside from theability to modify the coefficients of the “fax” algorithm, there is noflexibility in the modem algorithm to allow it to perform tasks otherthan facsimile data recovery. This results in a high-cost,application-specific system architecture with redundant processingcapabilities.

A variation in the Rockwell and Yamaha modem architectures isexemplified by the OKI KV96-X6D modem chip set. While the architectureof the OKI modem chip set maintains the separate modem and generalpurpose processor functions of the Rockwell and Yamaha modems describedabove, its analog front end and DSP functions are also separated. Sincethe DSP function is programmable, some flexibility in the type of signalthat may be processed is permitted. However, once programmed, the DSPfunction of the OKI modem still relies on a fixed DSP algorithm. Thus,the OKI architecture has the same basic limitations and inefficiecies asthe Rockwell and Yahama devices.

The Texas Instruments TMS320C25 Digital Signal Processor provides a“general purpose” DSP capability in that it can accommodate a number ofDSP algorithmic sequences. However, it relies on dedicated memory forstorage of its DSP operations and data. Thus, it must incorporate itsown segregated control capability aside from that provided by thegeneral purpose processor with which it is associated.

NEC IC Microsystems Ltd. provides a modem DSP chip that includes a DSPcore that is integrated with a general purpose processor block. However,the DSP core of the NEC device is dedicated to a particular algorithmand relies on its own control functions and an internal memory separatefrom that of the general purpose processor function for storage andretrieval of its operation. Furthermore, the general purpose processorfunction is fully embedded, making it unavailable for tasks other thanthose related to the dedicated DSP function.

It would, therefore, be desirable to have available a dual processorplatform that can execute a variety of DSP algorithms while maintainingfull general purpose processor capability.

SUMMARY OF THE INVENTION

The present invention provides a data processing system that utilizesintegrate general purpose processor (GPP) and digital signal processor(DSP) functions that are connected for common access to an internalshared memory array. The shared memory array stores the operands for aset of basic DSP operations that can be executed by the DSP function.The sequence of DSP operations to be executed by the DSP function isselectively configurable by the GPP function; that is, the generalpurpose processor can define a variety of DSP algorithms that can beexecuted by the DSP function for processing different digital inputsignal formats. In addition to storing the operands required by the DSPfunction for execution of a DSP algorithm, the internal shared memoryarray also stores selected instructions and data required by the GPPfunction for execution of general purpose tasks. The operands,instructions and data may be selectively loaded to the internal sharedmemory array from system memory. After execution of a DSP algorithm, thecorresponding information set may be down-loaded from the internalmemory array to system memory and a new information set retrieved forexecution of a subsequent DSP algorithm or a new general purposeprocessor task.

Thus, in accordance with the principles of the present invention, thegeneral purpose processor selects a DSP algorithm for conditioning andrecovering digital data from the incoming signal. That is, the GPPselects from the set of basic DSP operations to define a specificsequence of DSP operations appropriate for processing the incomingsignal. The GPP then retrieves operands required for execution of theselected DSP algorithm and/or instructions and data critical to the GPPfor controlling the DSP function or for performing GPP tasks and loadsthem into the internal shared memory array. Next, the GPP invokes thefirst DSP operation in the selected sequence and the DSP functionperforms the DSP operation utilizing operands retrieved by the DSPfunction from both the shared memory array and system memory. Uponcompletion of the DSP operation by the DSP function, the GPP functioneither reads the result of the DSP operation, invokes the next DSPoperation in the selected sequence or performs a GPP task. This processcontinues until the selected sequence of DSP operations has beenexecuted by the DSP function. The GPP may then download from theinternal shared memory array the operands, instructions and datautilized in executing the selected DSP algorithm and either identify andexecute a subsequent DSP algorithm fashioned from the set of basic DSPoperations or retrieve instructions and data required for a separate GPPtask.

While the input signal to the data processing system may be receiveddirectly from a digital source, a preferred embodiment of the inventionincludes an analog front end that converts a modulated input signalreceived on an analog channel to a corresponding digital signal forprocessing by the data processing system.

Thus, a data processing system in accordance with the present inventionprovides a unique system partitioning by integrating a small DSP moduleand a general purpose processor. This unique partitioning provides asingle processor solution for both DSP and general purpose computationsthat can utilize the same programming mode and the same systemdevelopment tools for both functions. The DSP module provides thecapability necessary to handle a variety of DSP requirements. Theinternal shared memory allows the DSP algorithms to be tuned or changedor new algorithms to be added to meet changing, expanding systemrequirements; general purpose computation intensive tasks can also beexecuted directly from the internal shared memory.

A better understanding of the features and advantages of the presentinvention may be obtained by reference to the following detaileddescription of the invention and accompanying drawings which set forthan illustrative embodiment in which the principles of the invention areutilized.

DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating the basic functional partitioningof a conventional facsimile system.

FIG. 2 is a block diagram illustrating the basic functional partitioningof a data processing system in accordance with the present invention.

FIG. 3 is a block diagram illustrating the primary functional units of adata processing system in accordance with the present invention,

FIG. 4 is a block diagram illustrating a DSP module utilizable in a dataprocessing system in accordance with the present invention.

FIG. 5 illustrates the general purpose processor address mapping of adata processing system in accordance with the present invention.

FIG. 6 is a table illustrating the memory organization of a complexvector for use in a DSP module in accordance with the present invention,

FIG. 7 provides an instruction set summary for a DSP module inaccordance with the present invention,

FIG. 8 is a table illustrating the handling of cyclic buffers for a DSPmodule in accordance with the present invention,

FIG. 9A is a block diagram illustrating an internal bus configuration ofa data processing system in accordance with the present invention withthe DSP module executing a VCMAG command.

FIG. 9B is a block diagram illustrating an internal bus configuration ofa data processing system in accordance with the present invention withthe DSP module executing a VCMAD, VCMUL or VCMAC command,

FIG. 9C is a block diagram illustrating an internal bus configuration ofa data processing system in accordance with the present invention withthe general purpose processor executing a read or write to registers ofthe DSP module or to the internal memory array.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 2 shows a data processing system 10 which is uniquely partitionedin accordance with the concepts of the present invention. The dataprocessing system 10 is described below in context of the requirementsof a facsimile system. However, it will be understood by those skilledin the art that the principles of the invention are applicable to anysystem which receives an incoming data signal that requires digitalsignal processing.

The data processing system 10 shown in FIG. 2 includes two primaryfunctional elements: an analog front end 12 and an integrated processingplatform 14. The integrated processing platform 14 includes both adigital signal processor (DSP) module 16 and a general purpose processor(GPP) 18.

The analog front end 12 converts a modulated input signal received froman analog transmission channel, e.g. a telephone line, to a digitizedreplica of the modulated input signal. The analog front end 12 can beimplemented utilizing conventional, off-the-shelf integrated circuitproducts available for this purpose.

As stated above, the integrated processor platform 14 includes a DSPmodule 16 that recovers digital data from the digital signal generatedby the analog front end 12. The DSP module 16 includes a processingmechanism, described in greater detail below, that conditions thedigital signal utilizing an algorithm comprising a selected sequence ofDSP operations.

The general purpose processor 18 controls the DSP module 16 andprocesses the digital data generated by the DSP module 16 to a desiredend result. The general purpose processor 18 may be any conventionalstate-of-the-art microprocessor.

As further shown in FIG. 2, while in many applications, the analog frontend 12 will be utilized to convert a modulated input signal received onan analog channel to a corresponding digital signal, there are a growingnumber of applications (e.g., ISDN and T1) in which a digital inputsignal will be received by the integrated processor platform 14 directlyfrom a digital source.

Referring to FIG. 3, both the DSP module 16 and the general purposeprocessor 18 are connected to an internal bus 20, allowing both the DSPmodule 16 and the general purpose processor 18 to communicate with asystem memory (not shown) via a conventional bus interface unit 24 fortransfer of control/status information and address/data therebetween. Itwill be understood by those skilled in the art that the internal bus 20comprises both an internal address bus for handling address referencesby the DSP module 16 and the general purpose processor 18 and aninternal data bus for handling instruction and data transfers.

To save bus bandwidth, the DSP module 16 stores operands used inexecuting DSP algorithms in an internal RAM memory array 22 which, aswill be described in greater detail below, is also accessible to generalpurpose processor 18. That is, in accordance with the concepts of thepresent invention, the internal memory array 22 serves as a sharedresource for both the DSP module 16 and the general purpose processor18. In the illustrated embodiment, the internal memory is shown asaccessible by the DSP module 16 and the general purpose processor 18 viathe internal bus 20. It will be understood by those skilled in the artthat other bus structures would also provide the desired sharedaccessibility to the internal memory array 22; for example, the internalmemory array 22 could be implemented as a dual port memory.

As described in greater detail below, the DSP module 16 may fetchoperands in parallel from the internal memory array 22 and systemmemory.

The DSP memory 16 executes vector operations on complex variables thatare optimized for DSP applications. The general purpose processor 18treats the DSP module 16 as a memory mapped I/O device that occupies areserved memory space, interfacing with the DSP module 16 via a set ofmemory mapped registers.

As shown in FIG. 4, high performance is achieved in the DSP module 16 byusing the internal shared memory array 22 as well as amultiplier/accumulator 26. The DSP module also includes its own internaladdress generator 28 for system memory and internal operand accesses,thus reducing the load on the general purpose processor 18. Both themultiplier/accumulator 26 and the address generator 28 are conventionalimplementations.

In the operation of the data processing system 10, the general purposeprocessor 18 selects from a basic set of DSP operations to define aspecific sequence of operations as the DSP algorithm to be executed bythe DSP module 16 for recovering data from the incoming digital signal.The general purpose processor then retrieves operands required forexecution of the selected DSP algorithm and/or instructions and datacritical to the general purpose processor for controlling the DSP module16 or for performing general purpose tasks and loads them into theinternal RAM array 22. The general purpose processor then invokes thefirst DSP operation in the selected sequence by issuing thecorresponding command to the control register of the DSP module 16. TheDSP module then places the general purpose processor 18 in a continuouswait state while it performs the first DSP operation utilizing operandsretrieved by the address generator 28 from the RAM array 22 and systemmemory. Upon completion of the DSP operation, the DSP module cancels thecontinuous wait state and the general purpose processor 18 then eitherreads the status of the DSP module 16 or the result of the DSP operationor carries on with the execution of its normal program flow, which maybe either invoking the next DSP operation in the selected sequence byissuing the appropriate command to the DSP module control register orperformance of a general purpose task. This process continues until theselected sequence of DSP operations has been completed. The generalpurpose processor may then download the contents of the shared internalRAM array 22 and retrieve a new set of operands, instructions and datafor further DSP operations or general purpose processing tasks.

As further shown in FIG. 4, the DSP module 16 performs complexarithmetic calculations on two vector operands provided to themultiplier/accumulator 26 at Port Y and Port D. One vector is retrievedfrom the internal memory array 22. The other vector is either organizedas a circular buffer in the system memory (described in greater detailbelow) or retrieved from the internal memory array 22.

The DSP module 16 executes vector operations in a two stage pipeline.This allows for a significant performance enhancement as the fetch andexecution of operands for consecutive vector elements are performedsimultaneously rather than in a steady sequential manner. The DSP module16 can fetch up to two data elements at a time, using its addressgenerator 28 for system memory access and the internal array 22 for thesecond operand. While fetching operands for one vector element, the DSPmodule 16 performs the multiply and add operations on the previousvector element.

The DSP module 16 contains seven registers in addition to the RAM array22. These registers, as well as the internal memory array 22, areaccessed by the general purpose processor 18 as memory-mapped I/Odevices. As shown in FIG. 5, their associated addresses reside in theupper part of a 32-bit address range of general purpose processor 18.External memory locations are specified by the lower 24 address bits andmapped to the lower 16 megabyte of this address range.

Any reference by general purpose processor 18 to the registers of theDSP module 16 or to the internal memory array 22 is done using a busprotocol for internal control register access to enable externalobservability. This protocol is more fully described incommonly-assigned U.S. patent application Ser. No. 07/750,771, filedAug. 8, 1991, now U.S. Pat. No. 5,212,775, which is a continuation ofU.S. patent application Ser. No. 07/461,023, filed Jan. 4, 1990, by ZeevBikowsky and Dan Biran, titled METHOD AND APPARATUS FOR OBSERVINGMEMORY-MAPPED REGISTERS, now abandoned; the just-referencedBikowsky/Biran application is hereby incorporated by reference toprovide additional background information regarding the presentinvention.

Each storage location in the internal memory array 22 is 32 bits wideand holds one complex number.

As stated above, the internal memory array 22 is not limited to storageof filtering coefficients for a specific DSP algorithm. It can also beused as a fast, zero-wait state, integrated memory for storinginstructions and data utilized by the general purpose processor 18 aswell as for storing selected operands for use by the DSP module 16 forprocessing a variety of data signal formats.

The memory array 22 can be used for instruction fetches with only onerestriction: instructions must be loaded into the array 22 using wordaligned accesses. This can be achieved by moving the aligned double-wordfrom system memory to memory array 22. Data can also be stored in thememory array 22 with one restriction: storing data in the array 22 canbe done only if all the data is written using aligned word ordouble-word accesses.

Referring back to FIG. 4, the multiplier input register Y is a 32-bitregister that holds one complex operand. The multiplier input register Yis mapped into two consecutive words called Y0 and Y1.

The accumulator register A is a 32-bit register that holds one complexresult. The A register is mapped into consecutive words, also called A0and A1. Internally, A0 and A1 are 32-bit registers. However, only bits15-30 (i.e., 16 bits) are visible. The rest of the bits are used for ahigher dynamic range and intermediate calculations.

A 24-bit pointer to the beginning of the data vector in the externalsystem memory is provided by data pointer register DPTR. In order toimplement circular buffers, only the less significant bits of the DPTRpointer are incremented. When the end of a buffer is reached, the leastsignificant bits of the DPTR pointer are reloaded with zeroes. Thenumber of bits that are set to zero, which defines the size of thecircular buffer, is controlled by a Control Register CTL, which isdescribed below. The least significant word of the DPTR pointer iscalled DPTR0 and the most significant byte is called DPTR1.

The CPTR registers holds the address and length of the coefficientvector.

The Control Register CTL controls the various modes of operation of thedata processing system 10.

The Status Register ST holds the status of the last vector operation.

The ST register is cleared to 0 in the following cases:

-   the user writes directly to either A0 or A1.-   the user writes to the CTL register upon reset.

The operation of the DSP module 16 will now be described in greaterdetail; the following terms will be used in the operational description:

C[i] an entry in internal memory array 22, entry [i] can be selected byaddress generator 28 or directly accessed by CPU 18; D[i] Data fromsystem memory fetched using address generator 28; Y Complex Multiplierinput register 30 in FIG. 4; D[i]* The conjugate of D[i]; A ComplexAccumulator register.

The DSP module 16 executes the following six basic commands:

VCMAC Vector Complex Multiply Accumulate VCMAG Vector Complex MagnitudeVCMAD Vector Complex Multiply Add VCMUL Vector Complex Multiply LOADWrite into C, Y, A or CTL STORE Read from C, Y, A, ST or CTL

The VCMAC, VCMAD and VCMUL commands use the following parameters:

D Vector Start Address in system memory C Vector Start Address ininternal RAM Vector Length Control bits

The VCMAG command uses only the last three operands.

Complex numbers are organized in the internal memory array 22 as doublewords. Each double word contains two 16-bit 2's complement fractionalintegers. The less significant word contains the Real part of thenumber. The most significant word contains the Imaginary part of thenumber.

The complete vectors utilized by the DSP module 16 consist of arrays ofcomplex numbers stored in consecutive addresses. Complex vectors must bealigned to double word boundary. FIG. 6 illustrates the memoryorganization of a vector D.

Referring back to FIG. 4, the arithmetic logic unit 26 of the DSP module16 contains a 16×16 multiplier 26a and a 32-bit adder/accumulator 26b.Bits 15-30 (16 bits) of the result are rounded and can be read byaccessing the A register. If an overflow is detected during anoperation, the Status Register (ST) overflow bit and either the OP0 bitor the OP1 bit is set to “1.”

When data is loaded into the adder/accumulator 26b, the 16 bits of dataare loaded into bits 15-30, the lower bits are set to “0”, while bit 31gets the same value as bit 30 (sign extended). An overflow is detectedwhenever the value of bit 30 is different from the value of bit 31.

Each basic DSP operation or instruction to be performed by the DSPmodule 16 is controlled by two OP-code bits (OPC0 and OPC1) and twospecifiers (COJ and CLR). COJ specifies whether the operand on port D ofthe multiplier 26a must be conjugated prior to multiplication. The CLRbit is used to extend the instruction set. On VCMAC and VCMAG, CLRspecifies whether the accumulator 26b must be cleared at the beginningof the vector operation. On VCMAD, CLR specifies that the operation willignore the value of C[i]. In VCMUL, CLR indicates that the value of D[i]is to be taken instead of 1+D[i].

FIG. 7 provides a summary of the set of basic DSP operations executed bythe DSP module 16 as function of the OPC1, OPC0, COJ, and CLR bits inthe CTL register. In FIG. 7, “SIGMA” represents the summation sign:$\sum\limits_{i = 1}^{M}\quad$

All the operands are complex numbers. Thus, A=SIGMA C[i]×D[i] breaksdown to:Re(A)=Sigma{Re(C[i]×Re(D[i])+Im(C[i]×Im(D[i])}Im(A)=Sigma{Re(C[i]×Im(D[i])+Im(C[i]×Re(D[i]}

The accumulator 26b, the multiplier input register Y, the external datapointer DPTR and the coefficient pointer CPTR registers are used astemporary registers during vector operations. Values stored in theseregister prior to activation of the DSP module 16 are destroyed. If thecontent of the accumulator register A after an operation of the DSPmodule 16 is used as an initial value for the next operation, it must beremembered that the least significant bits of (0/14) may contain a valueof other than zero.

As stated above, the DSP module 16 accesses arrays of data in externalmemory using the DPTR pointer as an address. The DS0 and DS1 bits of theCTL register control the size of the array. The DSP module 16 allows aconvenient way of handling data arrays as a FIF0. Only the appropriatenumber of the least significant bits of the DPTR are incremented on eachaccess. The upper bits remain constant. FIG. 8 shows which bits areincremented. The rest remain constant.

FIG. 9A illustrates the operation of the data processing system 10 withthe DSP module 16 exeucting the VCMAG command while the general purposeprocessor 18 executes a general purpose task.

As shown in FIG. 9A, bidirectional switches S that are responsive tocontrol signals provided by the general purpose processor 18 are locatedon the internal bus 20 so as to permit configuration of a variety ofcommunication paths among the DSP module 16, the general purposeprocessor 18 and the bus interface unit 24 (which, as stated above,provides access to external memory).

When the DSP module 16 is executing the VCMAG command, the DSP module 16is ,isolated from the internal bus 20 so that the address generator 28can retrieve operands for the VCMAG operation from the internal memoryarray 22 for both port Y and port D of the multiplier/accumulator 26.Isolation of the DSP module 16 in this manner allows the general purposeprocessor 18 to reference the external memory via the bus interface unit24 to allow transfer of data and instructions between the generalpurpose processor 18 and external memory for simultaneous execution of ageneral purpose task.

FIG. 9B illustrates the bus configuration during execution of the VCMAD,VCMUL or VCMA commands by the DSP module 16. In this case, the addressgenerator 28 references an operand stored in the memory array 22 whichis then provided to the Y port of the multiplier/accumulator 26. Theaddress generator 28 also references a location in external memory whichprovides the second operand to the D port of the multiplier/accumulator26. The general purpose processor 18 is isolated from both the internalmemory array 22 and external memory.

FIG. 9C illustrates read and write operations by the general purposeprocessor 18 either to the Y register or the accumulator register A orto the internal memory array 22 of the DSP module. As shown in FIG. 9C,in this case, the general purpose processor 18 references the selectedstorage elements as memory mapped I/O via the internal address bus andeither reads or writes to the selected storage elements via the internaldata bus.

Addition information regarding the present invention is provided inNational Semiconductor Corporation's Advanced Data Sheet, NS32FX16, HighPerformance Fax Processor, which is provided as Appendix at the end ofthis Detailed Description of the Invention.

It should be understood that various alternatives to the embodiments ofthe invention described herein may be employed in practicing theinvention. It is intended that the following claims define the scope ofthe invention, that the structure and methods within the scope of theseclaims and their equivalence be covered thereby.

1. A data processing system for processing a digital signal, the dataprocessing system comprising: a shared bus for transferring both dataand instructions; a shared memory array for storing both data andgeneral purpose instructions and that is connected for transfer of bothdata and general purpose instructions between the shared bus and theshared memory array; a digital signal execution unit connected to theshared bus for processing the digital signal utilizing both datatransferred between the shared memory array and the digital signalexecution unit on the shared bus and a selected sequence of individualdigital signal processor (DSP) instructions, the selected sequence ofDSP instructions consisting of individual general purpose instructionstransferred between the shared memory array and the digital signalexecution unit on the shared bus; and a general purpose processorconnected to the shared bus for controlling the digital signal executionunit by selecting each general purpose instruction to be transferred tothe digital signal execution unit from the shared memory array wherebythe selected sequence of individual DSP instructions executed by thedigital signal execution unit is selectively configurable by the generalpurpose processor.
 2. An integrated circuit data processing system forprocessing a digital signal, the data processing system comprising; ashared internal bus for transferring both general purpose instructionsand data; a shared bus interface unit connected to the shared internalbus and connectable via a shared external bus to a shared externalmemory array via an external input/output port of the shared externalmemory array such that general purpose instructions and data stored inthe shared external memory array may be transferred via externalinput/output port to be shared internal bus via the shared bus interfaceunit; a digital signal execution unit connected to the shared internalbus for processing the digital signal utilizing both data transferred tothe digital signal execution unit from the shard external memory arrayvia the shared internal bus and a selected sequence of individualdigital signal processor (DSP) instructions, the selected sequence ofDSP instructions consisting of individual general purpose instructionstransferred to the digital signal execution unit from the sharedexternal memory array via the shared internal bus; and a general purposeprocessor connected to the shared internal bus for controlling thedigital signal execution unit by selecting each of the general purposeinstructions to be transferred to the digital signal execution unit fromshared external memory array via the shared internal bus whereby theselected sequence of individual DSP instructions executed by the digitalsignal execution unit is selectively configurable by the general purposeprocessor.
 3. An integrated circuit data processing system as in claim 2and further comprising a shared internal memory array connected to theshared internal bus via an internal input/output port of the sharedinternal memory array such that general purpose instructions and datastored in the shared internal memory are transferred via the internalinput/output port of the shared internal memory array to the sharedinternal bus for transfer to either the digital signal execution unit orthe general purpose processor whereby the selected sequence ofindividual DSP instructions executed by the digital signal executionunit is selectively configurable by the general purpose processorselecting individual general purpose instructions from the sharedexternal memory and/or the shared internal memory.
 4. A data processingsystem for processing a digital signal, the data processing systemcomprising: a shared bus for transferring both data operands and generalpurpose instructions; a shared memory array for storing both dataoperands and general purpose instructions and that is connected fortransfer of data operands and general purpose instructions between theshared bus and the shared memory array; a digital signal execution unitconnected to the shared bus for processing the digital signal utilizingdata operands transferred from the shared memory array to the digitalsignal execution unit on the shared bus and a selected sequence ofindividual digital signal processor (DSP) instructions, the selectedsequence of DSP instructions consisting of individual general purposeinstructions transferred from the shared memory array to the digitalsignal execution unit on the shared bus; and a general purpose processorconnected to the shared bus for controlling the digital signal executionunit by selecting each general purpose instruction to be transferred tothe digital signal execution unit from the shared memory array; andwherein the digital signal execution unit includes a control registerconnected to the shared bus for storing a general purpose instructiontransferred to the digital signal execution unit by the general purposeprocessor from the shared memory array on the shared bus; amultiply/accumulate unit that responds to storage of said generalpurpose instruction in the control register by initiating execution of aDSP operation corresponding to said general purpose instruction; and aDSP address generator connected to the shared bus for retrieving a firstdata operand stored in the shared memory and utilizable by themultiply/accumulate unit in executing said DSP operation.
 5. A dataprocessing system as in claim 4 wherein the multiply/accumulate unitincludes first and second input ports for receiving said first dataoperand and a second data operand respectively, for utilization by themultiply/accumulate unit in executing said DSP operation.
 6. A dataprocessing system as in claim 5 wherein the address generator includesmeans for retrieving both said first data operand and said second dataoperand from the shared memory array via the shared bus.
 7. Anintegrated circuit data processing system for processing a digitalsignal, the data processing system comprising: (a) a digital signalexecution unit that recovers digital data from the digital signal byexecuting a selected sequence of digital signal processor (DSP)instructions; (b) a general purpose processor that selects the sequenceof DSP instructions for execution by the digital signal execution unitfrom a set of DSP instructions and that performs general purposeprocessing tasks by executing general purpose instructions utilizingselected data; (c) a shared internal bus for transferring both data andinstructions and to which both the digital signal execution unit and thegeneral purpose processor are connected; and (d) a shared internalmemory array connected to the shared internal bus via an internalinput/output port of the shared internal memory array such that theshared internal memory array is accessible by the digital signalexecution unit via the internal input/output port for transferringoperands utilizable by the digital signal execution unit between theshared internal memory array and the digital signal execution unit onthe shared internal bus and such that the shared internal memory arrayis accessible by the general purpose processor via the internalinput/output port for transferring the general purpose instructions andthe selected data between the shared internal memory array and thegeneral purpose processor on the shared internal bus; and (e) a sharedbus interface unit connected between the shared internal bus and ashared external system memory that stores operands, instructions anddata for implementing the transfer of operands, instructions and databetween the shared internal bus and the shared external system memorysuch that the digital signal execution unit and the general purposeprocessor may access either the shared internal memory via the internalinput/output port of the shared internal memory or the shared externalmemory system via the shared bus interface unit.
 8. A data processingsystem as in claim 7 wherein the digital signal execution unit includesan internal address generator for retrieving operands from either theshared internal memory array or the external memory system via theshared internal bus for use by the digital signal execution unit inexecuting the selected sequence of DSP instructions.
 9. An integratedcircuit data processing system for processing a digital signal, the dataprocessing system comprising: (a) a digital signal execution unit thatrecovers digital data from the digital signal by executing a selectedsequence of digital signal processor (DSP) instructions; (b) a generalpurpose processor that selects the sequence of DSP instructions forexecution by the digital signal execution unit from a set of DSPinstructions and that performs general purpose processing tasks byexecuting general purpose instructions utilizing selected data; (c) ashared internal bus for transferring both data and instructions and towhich both the digital signal execution unit and the general purposeprocessor are connected; and (d) a shared internal memory arrayconnected to the shared internal bus via an internal input/output portof the shared internal memory array such that the shared internal memoryarray is accessible by the digital signal execution unit via theinternal input/output port for transferring operands utilizable by thedigital signal execution unit between the shared internal memory arrayand the digital signal execution unit on the shared internal bus andsuch that the shared internal memory array is accessible by the generalpurpose processor via the internal input/output port for transferringthe general purpose instructions and the selected data between theshared internal memory array and the general purpose processor on theshared internal bus; wherein the digital signal execution unit includesan internal address generator for retrieving operands from the sharedinternal memory array via the shared internal bus for use by the digitalsignal execution unit in executing the selected sequence of DSPinstructions.
 10. An integrated circuit data processing system forprocessing a digital signal, the data processing system comprising: (a)a digital signal execution unit that recovers digital data from thedigital signal by executing a selected sequence of digital signalprocessor (DSP) instructions; (b) a general purpose processor thatselects the sequence of DSP instructions for execution by the digitalsignal execution unit from a set of DSP instructions and that performsgeneral purpose processing tasks by executing general purposeinstructions utilizing selected data; (c) a shared internal bus fortransferring both data and instructions and to which both the digitalsignal execution unit and the general purpose processor are connected;(d) a shared internal memory array connected to the shared internal busvia an internal input/output port of the shared internal memory arraysuch that the shared internal memory array is accessible by the digitalsignal execution unit via the internal input/output port fortransferring operands utilizable by the digital signal execution unitbetween the shared internal memory array and the digital signalexecution unit on the shared internal bus and such that the sharedinternal memory array is accessible by the general purpose processor viathe internal input/output port for transferring the general purposeinstructions and the selected data between the shared internal memoryarray and the general purpose processor on the shared internal bus;wherein the DSP instructions and the general purpose instructionscomprise subsets of a single instruction set executable by the dataprocessing system; and (e) an instruction sequencing unit connected tothe shared internal bus for controlling the flow of execution of the DSPinstructions and the general purpose instructions.
 11. A data processingsystem for processing a digital signal, the data processing systemcomprising: a shared bus that transfers data and instructions; a sharedmemory array that stores data and general purpose instructions and thatis connected to transfer data and general purpose instructions betweenthe shared bus and the shared memory array; a digital signal executionunit (DSEU) connected to the shared bus that processes the digitalsignal utilizing data transferred between the shared memory array andthe DSEU on the shared bus and a selected sequence of individual DSEUinstructions, the selected sequence of DSEU instructions includingindividual general purpose instructions transferred between the sharedmemory array and the DSEU on the shared bus; and a general purposeprocessor (GPP) connected to the shared bus for controlling the DSEU byselecting each general purpose instruction to be transferred to the DSEUfrom the shared memory array, the selected sequence of individual DSEUinstructions executed by the DSEU being selectively configurable by theGPP selecting individual general purpose instructions.
 12. The dataprocessing system of claim 11 wherein the DSEU has a register, andstarts execution of a general purpose instruction in response to the GPPloading information into the register.
 13. The data processing system ofclaim 11 wherein the GPP loads data into a location, and the DSEUretrieves data required by the instruction from the location.
 14. Thedata processing system of claim 11 wherein the DSEU places the GPP in acontinuous wait state while the DSEU executes the instruction.
 15. Thedata processing system of claim 11 wherein the GPP reads a status of theDSEU after the DSEU complete execution of the instruction.
 16. The dataprocessing system of claim 11 wherein the GPP reads a value that resultsfrom executing the instruction after the DSEU completes execution of theinstruction.
 17. The data processing system of claim 11 wherein the DSEUonly executes a single general purpose instruction when said informationis loaded into the register.